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================================
Circuiti digitali con Minetest
================================
-------------------------------------------------
Prepariamoci alla rivoluzione delle FPGA libere
-------------------------------------------------
Microcontrollori
----------------
.. image:: img/UnoConnections.jpg
:align: center
https://en.wikipedia.org/wiki/File:UnoConnections.jpg
FPGA
----
.. image:: img/icezum-alhambra-v1.1.jpg
:align: center
https://github.com/fpgawars/icezum/wiki
Pre-2016
--------
* Ambiente fossilizzato
* Strumenti complessi
Oggi
----
http://www.clifford.at/icestorm/
::
$ make
iverilog -o bpl_tb.out bpl.v bpl_tb.v
./bpl_tb.out
VCD info: dumpfile bpl_tb.vcd opened for output.
component ok
component ok
yosys -p 'synth_ice40 -blif bpl.blif' bpl.v
[...]
Domani
------
.. image:: img/icestudio.png
:align: center
https://github.com/FPGAwars/icestudio/blob/develop/doc/images/main.png
Minetest
--------
.. image:: img/minetest.png
:align: center
http://screenshots.debian.net/screenshots/000/014/670/large.png
Mesecons
--------
.. image:: img/mesecons.png
:align: center
http://screenshots.debian.net/screenshots/000/014/980/large.png
Minetest: informazioni e download
---------------------------------
* https://www.minetest.net/
* http://mesecons.net/
Numeri decimali
---------------
.. math::
123 = 1 * 10^2 + 2 * 10 + 3
Numeri binari
-------------
.. math::
1010 = 1 * 2^3 + 0 * 2^2 + 1 * 2 + 0
Porte logiche: AND
------------------
+---+---+---------+
| A | B | A AND B |
+===+===+=========+
| 0 | 0 | 0 |
+---+---+---------+
| 0 | 1 | 0 |
+---+---+---------+
| 1 | 0 | 0 |
+---+---+---------+
| 1 | 1 | 1 |
+---+---+---------+
Porte logiche: OR
-----------------
+---+---+--------+
| A | B | A OR B |
+===+===+========+
| 0 | 0 | 0 |
+---+---+--------+
| 0 | 1 | 1 |
+---+---+--------+
| 1 | 0 | 1 |
+---+---+--------+
| 1 | 1 | 1 |
+---+---+--------+
Porte logiche: NOT
------------------
+---+-------+
| A | NOR A |
+===+=======+
| 0 | 1 |
+---+-------+
| 1 | 0 |
+---+-------+
Porte logiche: XOR
------------------
+---+---+---------+
| A | B | A XOR B |
+===+===+=========+
| 0 | 0 | 0 |
+---+---+---------+
| 0 | 1 | 1 |
+---+---+---------+
| 1 | 0 | 1 |
+---+---+---------+
| 1 | 1 | 0 |
+---+---+---------+
Altre informazioni
------------------
* http://fpgawars.github.io/
* https://github.com/Obijuan/open-fpga-verilog-tutorial/wiki
Queste slide
------------
https://git.trueelena.org/cgit.cgi/docs/talks/
Licenza Creative Commons Attribution-ShareAlike 4.0 International License.
https://www.gl-como.it
|
